Patent Number: 6,295,226

Title: Memory device having enhanced programming and/or erase characteristics

Abstract: A semiconductor memory device includes an erase line, a common line, and a first transistor coupled between the conductive line and the common line. The memory device includes a plurality of memory cells and bit lines, each memory cell including a program line, a memory transistor, and a tunneling capacitor having a first node coupled to the floating gate. A second transistor is coupled between the program line and another node of the tunneling capacitor. An access transistor is coupled to the memory transistor and the bit line. The second transistor may be a depletion-type transistor, as may be the first transistor that is coupled to the erase line. The memory cell may also be implemented as a single-polysilicon memory structure.

Inventors: Yang; Hsu Kai (Pleasanton, CA)

Assignee: Kaitech Engineering, Inc.

International Classification: G11C 16/04 (20060101); H01L 27/115 (20060101); G11C 016/04 ()

Expiration Date: 09/25/2018