Patent Number: 6,295,227

Title: Non-volatile semiconductor memory device

Abstract: There is provided a NAND type EEPROM capable of setting a plurality of erase blocks in a single NAND cell block. The NAND cell block of a memory cell array comprises a NAND cell comprising a plurality of memory cell transistors connected in series between a bit line and a source line. Between the bit line and source line of the NAND cell, a selecting transistor is provided. A block dividing selecting transistor is provided between adjacent two memory transistors in the NAND cell, so that the NAND cell block is divided into two memory cell units. One of these memory cell units is selected as an erase unit to carry out the batch erase of data every erase unit and the write of data every page.

Inventors: Sakui; Koji (Setagaya-Ku, JP), Nakamura; Hiroshi (Kawasaki, JP)

Assignee: Kabushiki Kaisha Toshiba

International Classification: G11C 16/16 (20060101); G11C 16/04 (20060101); G11C 8/14 (20060101); G11C 8/00 (20060101); G11C 16/06 (20060101); H01L 27/115 (20060101); G11C 016/04 ()

Expiration Date: 09/25/2018