Patent Number: 6,295,229

Title: Semiconductor device and method of operating it

Abstract: A semiconductor device (70) includes a memory cell having a select transistor (67) and a storage transistor (65) having a relatively uniform tunnel dielectric thickness under both the floating gate (651) of the storage transistor and the select gate (671) of the select transistor (67). The select transistor (67) is adjacent to the drain region (68) for the memory cell to nearly eliminate a drain disturb problem. During programming, the control gate (652) is at a negative potential, and the drain region (68) is at a positive potential. The drain potential is sufficiently low to not degrade the tunnel dielectric layer (42) of the select transistor (67). During erase, a positive potential is applied to the control gate (652). The relatively uniform tunnel dielectric layer (42) thickness of the select transistor (67) allows for a faster operating device by increasing the read current of the memory device.

Inventors: Chang; Kuo-Tung (Austin, TX), Prinz; Erwin J. (Austin, TX), Swift; Craig T. (Austin, TX)

Assignee: Motorola Inc.

International Classification: G11C 16/04 (20060101); G11C 16/12 (20060101); G11C 16/06 (20060101); G11C 016/04 ()

Expiration Date: 09/25/2018