Patent Number: 6,295,231

Title: High-speed cycle clock-synchronous memory device

Abstract: A high-speed clock-synchronous memory device is provided with a sense amplifier S/A shared by and between cell arrays, and a cell array controller unit CNTRLi, wherein input and output of data/command synchronous with the clock, access command supplies all address data bits (row and column) simultaneously. By acknowledging a change in bits observed between two successive commands, regarding some of address bits configuring access address, the device judges whether the current access is made within the same cell array as the preceding access, between the neighboring cell arrays, or between remote cell arrays. According to the judgement, suitable command cycle is applied. At this time, the command cycle satisfies relationship: S.gtoreq.N.gtoreq.F.

Inventors: Toda; Haruki (Yokohama, JP), Tsuchida; Kenji (Kawasaki, JP), Kuyama; Hitoshi (Kawasaki, JP)

Assignee: Kabushiki Kaisha Toshiba

International Classification: G11C 11/408 (20060101); G11C 7/22 (20060101); G11C 7/00 (20060101); G11C 7/10 (20060101); G11C 007/00 ()

Expiration Date: 09/25/2018