Patent Number: 6,295,235

Title: Redundancy circuit of semiconductor memory

Abstract: A semiconductor has eight banks that can be accessed simultaneously. Within each bank, there are disposed two fixed spare row decoders and two mapping spare row decoders. Within each bank, two fixed fuse sets are provided corresponding to the fixed spare row decoders. Eight mapping fuse sets are provided at the outside of each bank, for example, with no association with the mapping spare row decoders. Each mapping fuse set stores mapping data for determining a correspondence of the mapping fuse set to a specific mapping spare row decoder within a specific bank.

Inventors: Nagai; Takeshi (Yokohama, JP)

Assignee: Kabushiki Kaisha Toshiba

International Classification: G11C 7/00 (20060101); G11C 11/34 (20060101); G11C 29/00 (20060101); G11C 5/00 (20060101); H01L 21/70 (20060101); H01L 21/82 (20060101); H01L 21/822 (20060101); H01L 27/04 (20060101); G11C 007/00 ()

Expiration Date: 09/25/2018