Patent Number: 6,295,236

Title: Semiconductor memory of the random access type with a bus system organized in two planes

Abstract: The semiconductor memory of the random access type has data lines, which can be connected to the local data lines in the memory cell array. The data lines are combined in groups and at least one group or individual data lines of the groups are formed by redundant data lines. Input/output lines lead from the memory in groups. A bus system organized in two planes is provided. The first plane is provided with bus lines which can be connected to all of the input/output lines, on the one hand, and to all of the data lines, on the other hand. The second plane has a plurality of individual partial buses, whose bus lines can be connected to in each case all of the data lines of at least two groups of data lines, on the one hand, and to all of the input/output lines of in each case one group, on the other hand.

Inventors: Brox; Martin (Munchen, DE), Pfefferl; Karl-Peter (Hohenkirchen-Siegergtsbrunn, DE)

Assignee: Infineon Technologies AG

International Classification: G11C 29/00 (20060101); G11C 007/00 ()

Expiration Date: 09/25/2018