Patent Number: 6,295,237

Title: Semiconductor memory configuration with a built-in-self-test

Abstract: A semiconductor memory configuration, in particular a DRAM, in which redundant memory cells, bit lines and word lines are determined for failed memory cells, failed word lines and failed bit lines by a built-in-self-test computing unit and a special algorithm.

Inventors: Pochmuller; Peter (Munchen, DE)

Assignee: Infineon Technologies AG

International Classification: G11C 29/44 (20060101); G11C 29/04 (20060101); G11C 29/00 (20060101); G11C 007/00 ()

Expiration Date: 09/25/2018