Patent Number: 6,295,238

Title: Semiconductor memory device having a circuit for fast operation

Abstract: A semiconductor memory device includes a command decoder receiving an external signal and issuing a command, a clock buffer receiving an external clock, gates and a refresh counter. When a test signal is at L-level, an auto-refresh signal is issued in accordance with the output of the command decoder. When the test signal is at H-level, the auto-refresh signal is issued in accordance with the output (external clock) of the clock buffer. Thereby, the test can be performed with a good timing accuracy even by a low-speed tester.

Inventors: Tanizaki; Tetsushi (Hyogo, JP), Dosaka; Katsumi (Hyogo, JP), Asakura; Mikio (Hyogo, JP)

Assignee: Mitsubishi Denki Kabushiki Kaisha

International Classification: G11C 11/406 (20060101); G11C 29/48 (20060101); G11C 29/04 (20060101); G11C 007/00 ()

Expiration Date: 09/25/2018