Patent Number: 6,295,239

Title: Control apparatus for testing a random access memory

Abstract: A logic device includes a RAM and control apparatus (10). The control apparatus (10) is adapted to receive input signals (6) from a processor and the control apparatus (10) is also adapted to be coupled to the RAM to send signals to the RAM in response to the input signals (6). The control apparatus (10) includes a data generator (3) and the data generator generates a test bit pattern which is dependent on the received input signals (6).

Inventors: Gopikuttan Nair; Vinod Nair (Singapore, SG)

Assignee: Infineon Technologies A.G.

International Classification: G11C 29/08 (20060101); G11C 29/16 (20060101); G11C 29/04 (20060101); G11C 007/00 ()

Expiration Date: 09/25/2018