Patent Number: 6,295,241

Title: Dynamic random access memory device

Abstract: Here is disclosed a dynamic semiconductor memory of high integrationdensity, which has parallel word lines and parallel bit lines formed on asubstrate. The bit lines include a pair of bit lines. A memory cell iscoupled to a word line and to one bit line of the bit-line pair. Thememory cell is composed of MOSFETs of a submicron size. A sense amplifiersection is connected to the pair of bit lines, and senses and amplifiesthe potential difference between the pair of bit lines in a data readoutmode. The amplifier section has a BIMOS structure, having MOSFETs andbipolar transistors. It has a driver section comprised of bipolartransistors.

Inventors: Watanabe; Shigeyoshi (Kanagawa-ken, JP), Fuse; Tsuneaki (Tokyo, JP), Sakui; Koji (Tokyo, JP), Ohta; Masako (Kanagawa-ken, JP), Oowaki; Yukihito (Kanagawa-ken, JP), Numata; Kenji (Kanagawa-ken, JP), Masuoka; Fujio (Kanagawa-ken, JP)


International Classification:

Expiration Date: 09/25/2013