Patent Number: 6,295,244

Title: Semiconductor memory device and data read method thereof

Abstract: The present invention discloses a semiconductor memory device. The device includes a plurality of memory cell array blocks; a predetermined number of main buffers for resetting a predetermined number of pairs of main data lines corresponding to a predetermined number of pairs of data items output from each of the plurality of memory cell array blocks in response to a main buffer control signal, and for generating a predetermined number of pairs of data when the data of each of the predetermined number of pairs of main data lines become complementary levels, the predetermined number of pair of data being reset after a lapse of predetermined time; a predetermined number of data output buffers for respectively receiving and buffering the predetermined number of pairs of data items generated by the predetermined number of main buffers, in response to a data output buffer control signal; and data output buffer control signal generating means for generating the data output buffer control signal, the data output buffer control signal being enabled in response to a control signal and disabled after a lapse of predetermined time from the point of time at which each of the pair of data items output from the predetermined number of main buffers reaches the desired complementary levels, thereby improving data read speed.

Inventors: Kim; Young Tae (Suwon, KR), Shin; Deok Joon (Seoul, KR)

Assignee: Samsung Electronics Co., Ltd.

International Classification: G11C 7/10 (20060101); G11C 008/00 ()

Expiration Date: 09/25/2018