Patent Number: 6,295,245

Title: Write data input circuit

Abstract: A write data input circuit for a double data rate (DDR) SDRAM acquires write data at both a rising and falling edge of a clock signal. The input circuit includes a command input buffer for receiving external commands, such as a read, write or refresh command. An external command latch circuit connected to the input buffer latches the external command in sync with a first clock signal. A decoder decodes the latched external command. A write determination circuit also receives the (undecoded) external command and generates an enable signal if the external command is a write command. A data input buffer is activated by the enable signal and receives write data. A data latch circuit latches the write data provided to the data input buffer in sync with a second clock signal.

Inventors: Tomita; Hiroyoshi (Kawasaki, JP), Kanda; Tatsuya (Kawasaki, JP)

Assignee: Fujitsu Limited

International Classification: G11C 11/4096 (20060101); G11C 11/409 (20060101); G11C 7/10 (20060101); G11C 013/00 ()

Expiration Date: 09/25/2018