Patent Number: 6,295,327

Title: Method and apparatus for fast clock recovery phase-locked loop with training capability

Abstract: A phase-locked loop with training capability that reduces the time for clock recovery of a clock signal at a known frequency embedded in a data signal. Prior to the data signal being available, the phase-locked loop, in a training mode, acquires frequency and phase lock with a local oscillator signal. As a result, the output of the PLL is frequency locked substantially at the frequency of the clock embedded in the expected data signal. To achieve this result, in the training mode, the PLL compares the local oscillator signal divided by a first divider with the output clock signal divided by a second divider. Then the frequency of the output clock signal of the PLL equals the frequency of the local oscillator multiplied by the ratio of the divisor of the second divider over the divisor of the first divider. When the data signal is available, the PLL operates in a data receiving mode. In that mode, the PLL typically only needs to acquire phase lock, since frequency lock already has been acquired in the training mode.

Inventors: Takla; Ashraf K. (San Jose, CA)

Assignee: Hitachi Micro Systems, Inc.

International Classification: H03L 7/10 (20060101); H03L 7/08 (20060101); H03L 7/18 (20060101); H03L 7/14 (20060101); H03L 7/16 (20060101); H04L 7/10 (20060101); H04L 7/033 (20060101); H04L 7/00 (20060101); H03D 003/24 ()

Expiration Date: 09/25/2018