Patent Number: 6,297,526

Title: Process for producing barrier-free semiconductor memory configurations

Abstract: Process for producing an integrated semiconductor memory configuration, in particular one suited to the use of ferroelectric materials as storage dielectrics, in which a conductive connection between one electrode of a storage capacitor and a selection transistor is not produced until after the storage dielectric has been deposited; and a semiconductor memory configuration produced using the production process.

Inventors: Hintermaier; Frank (Munchen, DE), Mazure-Espejo; Carlos (Zorneding, DE)

Assignee: Siemens Aktiengesellschaft

International Classification: H01L 21/70 (20060101); H01L 21/02 (20060101); H01L 27/115 (20060101); H01L 21/8242 (20060101); H01L 27/108 (20060101); H01L 21/8247 (20060101); H01L 027/108 ()

Expiration Date: 10/02/2018