Patent Number: 6,297,528

Title: Dual layer poly deposition to prevent auto-doping in mixed-mode product fabrication

Abstract: A new method of fabricating a capacitor and PMOS devices in a mixed-mode product production in which a composite polysilicon top plate electrode is provided which prevents out-diffusion of dopant from the capacitor plate so that there is no auto-doping of the PMOS channel region is described. A layer of gate silicon oxide is provided over the surface of a semiconductor substrate. A first polysilicon layer is deposited overlying the gate silicon oxide layer. The first polysilicon layer and gate oxide layer are etched away where they are not covered by a mask to provide a PMOS gate electrode in a first region of the wafer and a bottom plate electrode for the capacitor in a second region of the wafer. A capacitor dielectric layer is deposited over the surface of the wafer. A composite polysilicon layer is deposited overlying the capacitor dielectric layer wherein the composite polysilcon layer comprises a lower doped polysilcon layer and an upper undoped polysilicon layer. The composite polysilicon layer and capacitor dielectric layer are etched away where they are not covered by a mask to leave the capacitor dielectric layer and the composite polysilicon layer overlying the bottom plate electrode wherein the composite polysilicon layer forms the top plate electrode of the capacitor. The upper undoped polysilicon layer prevents out-diffusion from the lower doped polysilicon layer during thermal cycles thus preventing auto-doping.

Inventors: Chen; Chien-Feng (Hsin-Chu, TW), Chiou; Shyh-Perng (Hsin-Chu, TW)


International Classification: H01L 21/02 (20060101); H01L 27/06 (20060101); H01L 027/108 (); H01L 029/76 (); H01L 029/94 (); H01L 031/119 (); H01L 021/824 ()

Expiration Date: 10/02/2018