Patent Number: 6,297,529

Title: Semiconductor device with multilayered gate structure

Abstract: A semiconductor device is provided which is capable of suppressing an increase in the layer resistance of the gate electrode and preventing an increase of the contact resistance of the gate electrode with the silicide layer. The above properties of the semiconductor device are provided by forming the gate electrode comprising multiple layers, and the lowermost layer of the gate electrode is doped with an impurity, and other upper layers are formed undoped.

Inventors: Imai; Kiyotaka (Tokyo, JP)

Assignee: NEC Corporation

International Classification: H01L 21/02 (20060101); H01L 29/49 (20060101); H01L 21/28 (20060101); H01L 29/40 (20060101); H01L 21/336 (20060101); H01L 021/82 ()

Expiration Date: 10/02/2018