Patent Number: 6,297,530

Title: Self aligned channel implantation

Abstract: A short channel insulated gate field effect transistor has within the semiconductor body that houses the transistor a buried layer of the same conductivity type as the body but of higher impurity concentration. The buried layer is below the channel region and essentially extends only the distance between the drain and source regions of the transistor. The process to form the device provides high concentration in the region under the gate to suppress lateral depletion region expansion, while keeping a gradual junction in the vertical direction.

Inventors: Akatsu; Hiroyuki (Yorktown Heights, NY), Li; Yujun (Poughkeepsie, NY), Beintner; Jochen (Wappingers Falls, NY)

Assignee: Infineon Technologies North America Corp.

International Classification: H01L 21/70 (20060101); H01L 21/02 (20060101); H01L 21/336 (20060101); H01L 29/02 (20060101); H01L 21/8234 (20060101); H01L 29/10 (20060101); H01L 029/76 ()

Expiration Date: 10/02/2018