Patent Number: 6,297,533

Title: LDMOS structure with via grounded source

Abstract: A lateral conduction MOS structure characterized by reduced source resistance and reduced pitch. The structure includes a semiconductor substrate having an epitaxial semiconductor layer thereon, the substrate and epitaxial layer being of the same conductivity type. The structure further includes a source layer and a drain layer, each layer being of a second conductivity type, and a channel layer disposed between the source layer and the drain layer. The channel layer has an oxide layer and a gate disposed thereon. At least one of a wet anisotropic and a reactive ion etching step is performed to define a trench having a maximum width of about from 4-6 microns and a depth that extends well into the substrate. An electrically conductive via is then formed by deposition of metal into the trench to thereby establish a low resistance path between the source and the substrate ground.

Inventors: Mkhitarian; Aram (Glendale, CA)

Assignee: The Whitaker Corporation

International Classification: H01L 29/02 (20060101); H01L 29/417 (20060101); H01L 29/40 (20060101); H01L 29/10 (20060101); H01L 027/088 ()

Expiration Date: 10/02/2018