Patent Number: 6,297,534

Title: Power semiconductor device

Abstract: A first conductivity type active layer having high resistance is provided on an insulation region. A second conductivity type base layer is selectively formed on a surface of the first conductivity type active layer. A first conductivity type source layer is selectively formed on a surface of the second conductivity type base layer. A first conductivity type drain layer is selectively formed on a surface of the first conductivity type active layer. A gate electrode is formed facing, through a gate insulating film, a surface region of the second conductivity type base layer between the first conductivity type source layer and the first conductivity type active layer. A plurality of first and second conductivity type semiconductor regions are formed between the second conductivity type base layer and the first conductivity type drain layer. Each of the second conductivity type semiconductor regions is arranged alternately with each of the first conductivity type semiconductor regions. A drain current flows from the first conductivity type source layer to the first conductivity type drain layer through the first conductivity type semiconductor regions. Bottom portions of the second conductivity type semiconductor regions are shallower than the interface between the first conductivity type active layer and the insulation region. According to the present invention, low ON resistance and high withstand voltage are realized at the same time.

Inventors: Kawaguchi; Yusuke (Kanagawa-ken, JP), Nakamura; Kazutoshi (Kanagawa-ken, JP), Nakagawa; Akio (Kanagawa-ken, JP)

Assignee: Kabushiki Kaisha Toshiba

International Classification: H01L 29/66 (20060101); H01L 29/78 (20060101); H01L 29/02 (20060101); H01L 29/10 (20060101); H01L 029/76 ()

Expiration Date: 10/02/2018