Patent Number: 6,297,535

Title: Transistor having a gate dielectric which is substantially resistant to drain-side hot carrier injection

Abstract: A transistor fabrication process is provided which derives a benefit from having barrier atoms incorporated in a lateral area under a gate oxide of the transistor in close proximity to the drain. To form the transistor, a gate oxide layer is first grown across a silicon-based substrate. A polysilicon layer is then deposited across the gate oxide layer. Portions of the polysilicon layer and the oxide layer are removed to form a gate conductor and gate oxide, thereby exposing source-side and drain-side junctions within the substrate. An LDD implant is performed to lightly dope the source-side and drain-side junctions. An etch stop material may be formed upon opposed sidewall surfaces of the gate conductor, the upper surface of the gate conductor, and the source-side and drain-side junctions. Spacers may then be formed laterally adjacent the etch stop material located upon sidewall surfaces of the gate conductor. The unmasked portions of the source-side and drain-side junctions are heavily doped, resulting in source and drain regions that are aligned to the exposed lateral edges of the spacers. The drain-side spacer is removed and barrier atoms are forwarded through the exposed etch stop material and into a substrate/gate oxide interface region near the drain junction. The barrier atoms help reduce hot electron effects by blocking diffusion avenues of carriers (holes or electrons) from the drain-side junction into the gate oxide.

Inventors: Gardner; Mark I. (Cedar Creek, TX), Fulford, Jr.; H. Jim (Austin, TX)

Assignee: Advanced Micro Devices, Inc.

International Classification: H01L 21/02 (20060101); H01L 29/66 (20060101); H01L 21/336 (20060101); H01L 29/51 (20060101); H01L 21/28 (20060101); H01L 29/40 (20060101); H01L 29/78 (20060101); H01L 031/119 ()

Expiration Date: 10/02/2018