Patent Number: 6,297,543

Title: Chip scale package

Abstract: The present invention discloses a chip scale package. According to thisinvention, a lead frame 130 is bonded with an adhesive 140 to a bottomface of a semiconductor chip 110. An inner lead 131 of the lead frame 130is connected to a pad 111 of the semiconductor chip with a metal wire 120,and thickness of the inner lead 131 is equal to an original thickness ofthe lead frame 130. An outer lead 132 of the lead frame 130 is formed bypartially etching a bottom face of the lead frame 130. The entireresultant is encapsulated with a molding compound 100 such that the outerlead 132 is exposed therefrom, especially there is formed a downwardprotruding portion 101 at the molding compound 100 in the lower inner leadportion 131. This protruding portion raises the margin controlling thebonding height during the wire-bonding process such that the metal wire120 is not exposed from the molding compound 100. Furthermore, the outerleads 134 at both sides where no solder balls are mounted on, are exposedfrom the molding compound 100. The outer leads 132 at both sides beingexposed from the molding compound 100 act for dissipating outwardly heatthat is transmitted from the semiconductor chip 110 to the lead frame 130.A solder ball 150 is mounted at the inside of the outer lead 132 exposedfrom the molding compound 100.

Inventors: Hong; Sung Hak (Kyoungki-do, KR), Moon; Jong Tae (Chollabuk-do, KR), Park; Chang Jun (Kyoungki-do, KR), Choi; Yoon Hwa (Kyoungki-do, KR)


International Classification:

Expiration Date: 10/02/2013