Patent Number: 6,297,554

Title: Dual damascene interconnect structure with reduced parasitic capacitance

Abstract: An improved structure of a dielectric layer between two adjacent copper wiring lines is disclosed. The dielectric layer is composed of silicon oxide and the adjacent copper wiring lines are formed using a dual damascene process. The structure of the dielectric layer according to the present invention comprises at least one trench in the surface of the dielectric layer, an insulating layer in the trench and at least one void in the insulating layer. The void is used to reduce the effective dielectric constant as well as the parasitic capacitance of the dielectric layer.

Inventors: Lin; Min-Yi (Hsin-Chu, TW)

Assignee: United Microelectronics Corp.

International Classification: H01L 21/70 (20060101); H01L 23/532 (20060101); H01L 23/52 (20060101); H01L 21/768 (20060101); H01L 23/522 (20060101); H01L 023/48 ()

Expiration Date: 10/02/2018