Patent Number: 6,297,565

Title: Compatible IC packages and methods for ensuring migration path

Abstract: The present invention relates to integrated circuit packaging useful for programmable logic devices. The invention provides a migration path between a base integrated circuit and an extended integrated circuit that is a functional superset of the base. In the case of a programmable logic device (PLD), the pin element layout for a base integrated circuit provides for the connection of power, control, and I/O signals. Pins conducting power signals are located at the core of the base pin layout. Pins conducting control signals are located near the intersections of the horizontal and vertical axes of the layout and the perimeter of the layout. Remaining pins conduct I/O signals. The pin element layout for an extended integrated circuit subsumes the base pin element layout. Additional pins for conducting power signals are located near one or more diagonal axes of the extended pin element layout. Methods for determining an extended integrated circuit pin element layout starting from a base pin element layout are disclosed.

Inventors: Shiflet; Eric M. (Palo Alto, CA)

Assignee: Altera Corporation

International Classification: H01L 23/48 (20060101); H01L 23/50 (20060101); H01L 23/498 (20060101); H01L 023/48 ()

Expiration Date: 10/02/2018