Patent Number: 6,297,663

Title: Bus system

Abstract: A bus system has a bus constructed of a plurality of signal lines for transmission of signals, first and second terminating resistors provided at both ends of the respective signal lines, first, second and third modules coupled to the bus between the first and second terminating resistors and being each operative to transmit a signal through an output circuit of open drain type, first series resistors inserted in the respective signal lines between the first and second modules, and second series resistors inserted in the respective signal lines between the second and third modules.

Inventors: Matsuoka; Toshinobu (Tokyo, JP), Seki; Yukihiro (Yokohama, JP), Tobita; Tsunehiro (Yokohama, JP), Suzuki; Shinichi (Ebina, JP)

Assignee: Hitachi, Ltd.

International Classification: H04L 25/02 (20060101); H03K 017/16 (); H03K 019/003 ()

Expiration Date: 10/02/2018