Patent Number: 6,297,668

Title: Serial device compaction for improving integrated circuit layouts

Abstract: Techniques for providing improved memory flip-flops and other logiccircuits are described. A flip-flop uses only one p-channel transistor todrive the output node strongly to achieve fast results. To reducediffusion area, parallel logic is substantially eliminated and only seriesbranches are used, in critical areas. This allows all pull-up transistorsand/or all pull-down transistors to be formed from contiguous activeareas. The D-to-Q path is reduced, and the clock is used to control theoutput. The clock becomes the dominant controller of the output when it islocated closest to the output. Placing the clock devices closest to theclocked nodes reduces clock skew. The rising D response time and falling Dresponse time are caused to be as close as possible to reduce the overallcycle time. To reduce parasitics in the circuit, complex-gates are usedwhich are asymmetric. Even multiples of series branches per gate are usedto share contacts and eliminate breaks in the layout diffusion. Addingcomplex-gates to a circuit while using asymmetric gates for smallerlayouts achieves additional functionality. One component of the clock,along with the master drive circuit, is used to drive the slave latch of aflip-flop to avoid inserting additional gates into the logic of the fastoutput path. Reset and set circuitry is designed to be outside thecritical path of the clock, and outside the slave latch, to provide rapidQ output response time to the clock and D inputs.

Inventors: Schober; Robert C. (Huntington Beach, CA)

Assignee:

International Classification:

Expiration Date: 10/02/2013