Patent Number: 6,297,671

Title: Level detection by voltage addition/subtraction

Abstract: A circuit is designed with a first transistor (661) having a current path coupled between a supply terminal (32) and a first output terminal (665). A second transistor has a current path coupled between the first output terminal and a reference terminal. The current path of the second transistor current path has substantially the same width and length as the first transistor current path. A first comparator circuit (679, 685) has first (668) and second (23) input terminals and a second output terminal (681). The first input terminal is coupled to the first output terminal. The first comparator circuit produces a control signal in response to a voltage between the first and second input terminals. A generator circuit (80) receives the control signal and produces an output voltage at the supply terminal.

Inventors: Shih; Albert (Dallas, TX), Koelling; Jeffrey E. (Dallas, TX)

Assignee: Texas Instruments Incorporated

International Classification: G06F 1/26 (20060101); G11C 11/4074 (20060101); G11C 11/407 (20060101); G11C 5/14 (20060101); H03K 5/08 (20060101); G11C 16/06 (20060101); G11C 16/30 (20060101); H03K 005/22 (); H03K 005/153 ()

Expiration Date: 10/02/2018