Patent Number: 6,297,672

Title: CMOS integrated circuit

Abstract: In a ultra-large scale integrated circuit of CMOS structure, high speed operation can be performed without being affected by the wiring capacitance and the gate input capacitance. A current-output type gate is used as a transmitting gate 11, and a capacitor 54 is charged or discharged only during the transition time of a signal. The charge or discharge current is multiplied by current Miller circuits 55, 56 to supply the current to a conductive path 15. A current-input type gate is used as a receiving gate 31. This gate 31 is arranged such that the output and input ends of an inverter 35 of CMOS structure are interconnected, respective ends of the inverter to be connected to power supplies are connected to a positive power supply terminal 16 through the current Miller circuit of p-channel MOS.FETs 37, 39 and connected to a negative power supply terminal 17 through the current Miller circuit of n-channel MOS.FETs 38, 41 respectively, and the output ends of both the current Miller circuits are connected to the signal transmission path 15.

Inventors: Okayasu; Toshiyuki (Saitama, JP)

Assignee: Advantest Corporation

International Classification: H03K 19/0185 (20060101); H04L 25/02 (20060101); H02M 011/00 (); H03D 011/00 ()

Expiration Date: 10/02/2018