Patent Number: 6,297,674

Title: Semiconductor integrated circuit for low power and high speed operation

Abstract: In order to provide a semiconductor integrated circuit in which power consumption due to a leakage current in an active mode can be suppressed and which can operate at a high speed, the semiconductor integrated circuit includes: a first p-channel FET having a gate controlled by a first input and having a source-drain path connected between a first operating potential point and a first node; a first n-channel FET having a gate controlled by a second input and having a source-drain path connected between the first node and a second node; a second n-channel FET having a gate controlled by the first node and having a source-drain path connected between the second node and a second operating potential point; a third n-channel FET having a gate controlled by the first node and having a source-drain path connected between the second node and a third operating potential point; a second p-channel FET having a gate controlled by the first input and having a source-drain path connected between a third node and a fourth node; a third p-channel FET having a gate controlled by the fourth node and having a source-drain path connected between the first operating potential point and the third node; a fourth p-channel FET having a gate controlled by the fourth node and having a source-drain path connected between a fourth operating potential point and the third node; and a fourth n-channel FET having a gate controlled by the second input and having a source-drain path connected between the fourth node and the second operating potential point.

Inventors: Kono; Ichiro (Mitaka, JP), Yano; Kazuo (Hino, JP), Kato; Naoki (Kodaira, JP)

Assignee: Hitachi, Ltd.

International Classification: G11C 7/10 (20060101); G11C 5/00 (20060101); H01L 27/02 (20060101); H03K 19/00 (20060101); H03K 19/017 (20060101); H03K 19/01 (20060101); H03B 001/00 (); H03K 003/00 ()

Expiration Date: 10/02/2018