Patent Number: 6,297,680

Title: Internal clock generator that minimizes the phase difference between anexternal clock signal and an internal clock signal

Abstract: An internal clock generation circuit according to the present inventionincludes a phase comparator, a shift register, a filter, a monitorcircuit, and a plurality of delay lines such as first and second delaylines. The first delay line has delay steps each larger than that of thesecond delay line. The first delay line is first used to generate a clockminimized in phase difference with respect to an external clock. The clocksignal is inputted to the second delay line to perform fine adjustment tothe phase difference.

Inventors: Kondo; Takako (Tokyo, JP)


International Classification:

Expiration Date: 10/02/2013