Patent Number: 6,297,681

Title: Multi-cell delay generator device wherein the cells have transistor stacks and selective stack transistor bypasses

Abstract: A digital delay generator device is based on a series arrangement of cells, wherein each cell has a first input for receiving a single-phase clock signal, a second input for receiving a delayable signal for thereto imparting a cell delay, and an output for a so-delayed signal. Each cell comprising a series stack of transistors, and various cells comprise further transistor means for receiving a bypass control signal. Such further transistor means are arranged for under control of a bypass control signal effectively bypassing one or more cells to thereby effect a quantized overall delay shortening. In particular, such various cells form a contiguous pair in said string, and the transistor means effectively form respective transistor bypasses over clock-signal-controlled transistors in the associated series stack at mutually opposite sides of their respective stack.

Inventors: Wang; Zhenhua (Zurich, CH)

Assignee: U.S. Philips Corporation

International Classification: H03K 23/66 (20060101); H03K 23/00 (20060101); H03H 011/26 ()

Expiration Date: 10/02/2018