Patent Number: 6,297,688

Title: Current generating circuit

Abstract: MOS transistor P01 is connected between the supply terminal Vcc and node a. Resistor R1 is connected between the node a and the grounding terminal GND. MOS transistor P03 is used to reduce the consumed current when the circuit is not in operation. Differential amplifier cmp1 compares the potential in01 of the node a and reference potential Vref and applies a control signal to the gate of the MOS transistor so as to make the potential in01 of the node a equal to the reference potential Vref. At the same time, the control signal is also applied to the gate of MOS transistor P02. The MOS transistor P02 generates an electric current as a function of the electric current flowing to the MOS transistor P01.

Inventors: Nakamura; Hiroshi (Kawasaki, JP)

Assignee: Kabushiki Kaisha Toshiba

International Classification: G05F 3/08 (20060101); G05F 3/26 (20060101); G05F 001/10 (); G05F 003/02 ()

Expiration Date: 10/02/2018