Patent Number: 6,297,699

Title: Bias rail buffer circuit and method

Abstract: A bias rail buffer circuit and method in accordance with the present invention overcomes many shortcomings of the prior art. A bias rail buffer circuit for providing a reference signal is suitably configured to absorb external disturbances appearing on an output reference signal. A method for absorbing the external disturbances appearing at the output reference signal suitably includes the use of complementary transistors to source current and sink current to said output reference signal, depending on whether the external disturbances are providing a decrease or an increase to the output reference signal. The bias rail buffer circuit suitably includes an input transistor, a first pair of complementary transistors and a second pair of complementary transistors, such that the second pair of complementary transistors operate to source current and sink current to absorb external disturbances imparted on said output reference signal.

Inventors: Murray; Kenneth W. (Tucson, AZ), Halbert; Joel M. (Tucson, AZ)

Assignee: Texas Instruments Corporation

International Classification: H03F 3/30 (20060101); H03F 3/343 (20060101); H03F 3/45 (20060101); H03F 003/26 ()

Expiration Date: 10/02/2018