Patent Number: 6,297,702

Title: Phase lock loop system and method

Abstract: Symmetrical cross coupled PLL circuits provide pseudo-synchronizationbetween two independent clock signals, especially for use in faulttolerant applications. Independent oscillators provide input signals toeach of the PLL circuits. The PLL circuits include divide circuitry thatprovide output signals at some sub multiple of the input clock signals.The phase relationship between the output clock signals from the crosscoupled PLL circuits is monitored by phase detector circuits. If the phaseof one output clock signal is determined to be advanced relative to theother output clock signal, the phase of that output clock signal isretarded by temporarily increasing the divide ratio of the PLL circuitproducing the phase advanced signal.

Inventors: Locker; Kevin Wayne (Scottsdale, AZ), Murray; Joseph (Scottsdale, AZ)

Assignee:

International Classification:

Expiration Date: 10/02/2013