Patent Number: 6,297,974

Title: Method and apparatus for reducing stress across capacitors used in integrated circuits

Abstract: A method, apparatus, and system for controlling the voltage levels across capacitors coupled between a first node and a second node of an integrated circuit so that the voltage levels across these capacitors will not exceed the breakdown voltage limitation of these capacitors. The voltage level between the first and second nodes of the integrated circuit can vary from a second voltage level to a first voltage level when the integrated circuit transitions from a second power state to a first power state, respectively. A first capacitor and a second capacitor are connected in series between the first and second nodes of the integrated circuit forming a middle node between the first and second capacitors. The voltage level of the middle node is set to a third voltage level when the integrated circuit is placed in the first power state such that the voltage level between the first and middle nodes does exceed the breakdown voltage of the first capacitor and the voltage level between the middle and second nodes does not exceed the breakdown voltage of the second capacitor.

Inventors: Ganesan; Ramkarthik (Fair Oaks, CA), Jungroth; Owen W. (Sonora, CA)

Assignee: Intel Corporation

International Classification: H02M 3/07 (20060101); H02M 3/04 (20060101); H02M 003/18 (); H01G 009/10 (); G11C 007/00 ()

Expiration Date: 10/02/2018