Patent Number: 6,297,984

Title: Structure and method for protecting integrated circuits during plasma processing

Abstract: A protection circuit and method for preventing high word line voltages during plasma processing of integrated circuits. The protection circuit includes a shunt transistor connected between each word line and ground, and a light sensitive element connected to the gate of each shunt transistor. During plasma processing, the plasma glow activates the light sensitive element, which generates a corresponding voltage that is applied to a gate of the shunt transistors. Consequently, the built-up potentials in the word lines are shunted to ground throughout the plasma process.

Inventors: Roizin; Yakov (Atula, IL)

Assignee: Tower Semiconductor Ltd.

International Classification: H01L 27/115 (20060101); H01L 27/146 (20060101); H01L 27/02 (20060101); G11C 013/00 ()

Expiration Date: 10/02/2018