Patent Number: 6,297,992

Title: EPROM writing circuit

Abstract: An EPROM writing circuit including: a cell array consisting of an EPROMcell; a word line decoder and a bit line decoder for respectively decodingan address and a writing signal and enabling corresponding word lines andbit lines among a plurality of word lines and bit lines; a level sensingunit for sensing a level of an inputted booster voltage and outputting alevel sensing signal; a decoding unit for ANDing the level sensing signaland the writing signal and outputting it; a first, a second and a thirdpower switches enabled by the decoding signal, for supplying the sensedvoltage to a voltage distribution unit; a voltage distribution unitenabled by the output voltage of the power switches, for stepping down thebooster voltage to a different voltage level and outputting it; and aswitching unit for outputting the stepped-down voltage to the cell array,by which degradation of the EPROM gate due to the excessive writing whichis caused when the applied voltage Vpp is high is prevented and theproblem in that the writing time becomes excessively lengthened when theapplied voltage Vpp is low is automatically prevented.

Inventors: Oh; Hyung-Seog (Chungwon-Kun, KR)

Assignee:

International Classification:

Expiration Date: 10/02/2013