Patent Number: 6,297,996

Title: Test mode activation and data override

Abstract: A memory device with a test mode control circuit for entering a test moderesponsive to a high on the Vss pin or a low on the Vcc pin that supplypower to the output pins during normal operation of the memory device. Intest mode the wordlines and bitlines of the memory remain active from thetime they are activated, typically when the clock switched from a first toa second logic state, until the clock switches back to the first logicstate.

Inventors: McClure; David C. (Carrollton, TX)


International Classification:

Expiration Date: 10/02/2013