Patent Number: 6,297,999

Title: Semiconductor memory device and method for setting stress voltage

Abstract: The present invention provides a semiconductor memory device that performs a burn-in test. The device includes word lines, pairs of bit lines, memory cells, sense amplifiers connected to the pairs of bit lines for amplifying a potential difference between the associated pair of bit lines, and a burn-in test control circuit for providing a stress voltage to the plurality of word lines and the pairs of bit lines to perform a burn-in test based on the burn-in control signal The burn-in test control circuit includes a potential difference setting circuit for selecting one of the first word lines so to generate a potential difference between at least one of the pairs of bit lines. The sense amplifiers amplify the potential difference to provide the stress voltage between the word lines and the associated pair of bit lines and between the bit lines of that pair.

Inventors: Kato; Yoshiharu (Kasugai, JP), Kawamoto; Satoru (Kasugai, JP)

Assignee: Fujitsu Limited

International Classification: G11C 29/50 (20060101); G11C 29/04 (20060101); G11C 029/00 ()

Expiration Date: 10/02/2018