Patent Number: 6,298,002

Title: Memory structures having selectively disabled portions for power conservation

Abstract: An architecture for registers and/or memory may provide a selectively disable payload portion. The architecture induced energy conservation. The architecture may include two or more payload portions for storage of payload data and a portion for storage of administrative data. Based on the contacts of the administrative data, certain payload portions may be enabled or disabled.

Inventors: Brooks; David M. (Princeton, NJ), Tiwari; Vivek (Santa Clara, CA)

Assignee: Intel Corporation

International Classification: G11C 7/22 (20060101); G11C 7/00 (20060101); G11C 007/00 ()

Expiration Date: 10/02/2018