Patent Number: 6,298,003

Title: Boost circuit of DRAM with variable loading

Abstract: A boost circuit for driving word lines in a memory device, comprises: a delaying module for delaying signal to turn on a refresh cycle of the boost circuit; a precharge timing controlling module for controlling the timing of the refresh cycle, wherein the delay module transmitting the signal to the precharge timing controlling module for disabling and enabling the precharge timing controlling module; a precharge module for supplying charge to a first capacitor and a second capacitor, wherein the precharge module is controlled by the precharge timing controlling module; a first capacitor connected to the precharge module and charge the word lines for storing charges; when the precharge module stops to charge the first capacitor, the first capacitor starts to charge the word lines in 2k refresh mode and charge both of the word lines and the second capacitor in 4k refresh mode of the memory device; a second capacitor connected to the precharge module and charge the word lines for storing charges, wherein the second capacitor is connected to a controlling module for deciding to turn on the second capacitor, when the precharge module stops to charge the second capacitor, the second capacitor starts to charge the word lines in 2k refresh mode, but in 4k refresh mode of the memory device the first capacitor starts to charge the second capacitor and the word lines together.

Inventors: Chou; Min-Chung (Hsinchu, TW)

Assignee: Elite Semiconductor Memory Technology, Inc

International Classification: G11C 11/408 (20060101); G11C 11/4074 (20060101); G11C 7/22 (20060101); G11C 8/08 (20060101); G11C 7/00 (20060101); G11C 8/00 (20060101); G11C 11/407 (20060101); G11C 11/4076 (20060101); G11C 11/406 (20060101); G11C 008/00 ()

Expiration Date: 10/02/2018