Patent Number: 6,298,005

Title: Configurable memory block

Abstract: A circuit and method comprising a memory array and a plurality of address circuits. The memory may comprise a plurality of storage elements each configured to read and write data in response to an internal address signal. The plurality of address circuits may each be configured to generate one of said internal address signals in response to (i) an external address signal, (ii) a clock signal and (iii) a control signal.

Inventors: Landry; Greg J. (Merrimack, NH)

Assignee: Cypress Semiconductor Corp.

International Classification: G11C 8/00 (20060101); G11C 8/10 (20060101); G11C 008/00 ()

Expiration Date: 10/02/2018