Patent Number: 6,298,101

Title: Method and apparatus for accurately aligning a series of detection windows with a synchronization pattern in a data storage device

Abstract: An invention for more accurately initiating the generation of detection windows for detecting data within a stream of data pulses is disclosed. A high frequency clock, typically operating at rate corresponding to a multiple of the nominal clock rate (e.g., two or three times, is used for a portion of a decoder system. In one embodiment, a down counter and a detection window generation component of the decoder system are clocked at the higher rate, while the remaining elements are clocked at the nominal clock rate. In this manner, the detection windows are more accurately initiated, while the remaining portions of the decoder system do not require the extra expense imposed of operating at the higher clock rate. Using the present invention, synchronization delay is minimized and detection windows are more accurately aligned with data pulses which reduces the error rate and improves performance of the decoder system.

Inventors: Carlson; Lance Robert (Niwot, CO)

Assignee: Adaptec, Inc.

International Classification: G11B 20/14 (20060101); G11B 27/30 (20060101); H04L 7/04 (20060101); H04L 7/08 (20060101); H04L 027/06 (); H04C 007/00 ()

Expiration Date: 10/02/2018