Patent Number: 6,298,103

Title: Flexible clock and data recovery module for a DWDM optical communication system with multiple clock rates

Abstract: A Clock timing and Data Recovery (CDR) circuit for reconstructing a clock signal from a high speed data signal that contains no clock signal, such as data in a Non-Return-to-Zero format, and is particularly suitable for high data rate optical communication systems. The circuit uses a reference clock with a frequency that is sufficiently close to the data rate, to keep the circuit tuned to the correct frequency even when input data is absent. When input data is present, a quadrature downconverter mixes the reference clock with a series of pulses corresponding to the transition points of the data signal to produce two intermediate signals. These intermediate signals each go through baseband or intermediate band filters, whose outputs are then quadrature modulated to produce the correct output clock signal. Since the filters operate in a much lower frequency range than the associated data rate, the filters can be comparatively simple and economical, and exhibit superior resistance to aging and environmental effects. A wide range of data rates can be accommodated just by changing the frequency of the reference clock, without having to change the filter parameters. For networks that permit a variety of data rates to be used, automatic data rate detection can allow the correct reference clock frequency to be determined and selected for each incoming data message.

Inventors: Huang; Shouhua (San Clemente, CA), Goldberg; Bar-Giora (San Diego, CA)

Assignee: Sorrento Networks Corporation

International Classification: H04L 7/027 (20060101); H04L 7/033 (20060101); H04L 007/00 (); H03D 001/00 (); H04D 007/02 ()

Expiration Date: 10/02/2018