Patent Number: 6,298,105

Title: Method and apparatus for a low skew, low standby power clock network

Abstract: An apparatus for a low skew, low standby power clock network for a synchronous digital system. The power clock network comprises a reference network, maintaining a reference clock signal, and four clock spines, each with its own respective clock signal. To reduce clock skew within the power clock network (i.e., to keep the clock signals of the clock spines synchronous with the reference clock signal), the present invention employs the use of active and passive delay elements to compensate for such skew. A phase relation extraction logic compares the phase of the clock signals from each respective clock spine to the reference clock signal of the reference network. If it is determined that the clock signals of the spines lag the reference clock signal, the phase relation extraction logic will use an active control driver to "speed-up" the clock signals of the clock spines. And, if the clock signals of the clock spines lead the reference clock signal, the phase relation extraction logic will use capacitive loadings to "slow down" such clock signals. Advantageously, the likelihood of the microprocessor achieving its maximum operating potential is greatly enhanced by the synchronization of such signals.

Inventors: Dai; Xia (Fremont, CA), Geannopuolos; George (Portland, OR), Orton; John (Los Altos, CA), Wong; Keng (Portland, OR), Taylor; Greg F. (Portland, OR)

Assignee: Intel Corporation

International Classification: G06F 1/10 (20060101); G06F 1/32 (20060101); H03L 7/08 (20060101); H03L 7/087 (20060101); H03L 7/081 (20060101); H04L 001/00 (); H04L 025/00 (); H04L 025/40 ()

Expiration Date: 10/02/2018