Patent Number: 6,298,364

Title: Digital signal processing operation apparatus that allows combined operation

Abstract: When an instruction code CC that indicates by 1 instruction code a combined operation of an arithmetic operation and a shifting operation is applied to an instruction decoder, the decoder decodes the code CC, and provides an operation control signal S1 and a shift signal S3 to an operation unit and a shifter, respectively. The operation unit carries out an arithmetic operation on input data D1 and D2 according to a signal S1, whereby arithmetic operation resultant data is applied to the shifter via the selector as data having an operation precision greater than that of an eventual combined operation result. The shifter carries out a shifting operation on the input data according to a shift signal S3. Therefore, operation precision is ensured in the combined operation. Furthermore, two instructions of an arithmetic operation instruction and a shifting operation instruction are carried out in 1 instruction execution time, so that high speed operation is allowed.

Inventors: Kanekura; Hiroshi (Yamatokouriyama, JP)

Assignee: Sharp Kabushiki Kaisha

International Classification: G06F 7/38 (20060101); G06F 007/38 ()

Expiration Date: 10/02/2018