Patent Number: 6,298,367

Title: Floating point addition pipeline including extreme value, comparison and accumulate functions

Abstract: A multimedia execution unit configured to perform vectored floating point and integer instructions. The execution unit may include an add/subtract pipeline having far and close data paths. The far path is configured to handle effective addition operations and effective subtraction operations for operands having an absolute exponent difference greater than one. The close path is configured to handle effective subtraction operations for operands having an absolute exponent difference less than or equal to one. The close path is configured to generate two output values, wherein one output value is the first input operand plus an inverted version of the second input operand, while the second output value is equal to the first output value plus one. Selection of the first or second output value in the close path effectuates the round-to-nearest operation for the output of the adder. The execution unit may be configured to perform vectored addition and subtraction, integer/floating point conversion, reverse subtraction, accumulate, extreme value (minimum/maximum), and comparison instructions.

Inventors: Oberman; Stuart F. (Sunnyvale, CA), Juffa; Norbert (San Jose, CA), Weber; Fred (San Jose, CA), Ramani; Krishnan (Sunnyvale, CA), Krishna; Ravi (Milpitas, CA)

Assignee: Advanced Micro Devices, Inc.

International Classification: G06F 9/302 (20060101); G06F 7/48 (20060101); G06F 9/30 (20060101); G06F 7/57 (20060101); H03M 7/14 (20060101); H03M 7/24 (20060101); G06F 007/38 ()

Expiration Date: 10/02/2018