Patent Number:
6,298,369
Title:
High speed multiplier
Abstract:
The high speed multiplier takes advantage of results from previous calculations by recognizing that in many cases the multiplicand between a first and second multiplication differs only slightly. Thus, the present system divides the multiplicand into a cache lookup bit (CLB) and a table lookup bit (TLB). The results of a first multiplication are stored in a cache. The CLB of a of the multiplicand in the second multiplication is then compared to the CLB of the multiplicand in the second multiplication. If the CLB matches, the product of the first multiplication is retrieved. The product of the TLB of the multiplicand and the multiplier is then retrieved from a lookup table and either added or subtracted from the retrieved product.
Inventors:
Nguyen; Thi N. (Carrollton, TX)
Assignee:
STMicroelectronics, Inc.
International Classification:
G06F 7/48 (20060101); G06F 7/52 (20060101); G06F 007/52 ()
Expiration Date:
10/02/2018