Patent Number: 6,298,399

Title: System for managing input/output accesses at a bridge/memory controller having a status register for recording cause of interrupt

Abstract: An apparatus includes an input/output (I/O) address verification unit that determines whether an I/O address received from a processor is protected. An interrupt generator is coupled to the I/O address verification unit. The interrupt generator generates an interrupt if the I/O address is protected. An interrupt recorder is coupled to the address verification unit. The interrupt recorder records a cause of the interrupt.

Inventors: Martwick; Andrew (Folsom, CA)

Assignee: Intel Corporation

International Classification: G06F 13/20 (20060101); G06F 13/24 (20060101); G06F 12/08 (20060101); G06F 013/24 (); G06F 013/12 (); G06F 013/14 (); G06F 012/10 (); G06F 013/10 ()

Expiration Date: 10/02/2018