Patent Number: 6,298,407

Title: Trigger points for performance optimization in bus-to-bus bridges

Abstract: Method and apparatus for tuning the performance of bridge devices, including PCI-to-PCI bridges as well as PCI local bus bridges (or host bridges). The embodiments of the invention permit a multiple-bus computer system to be tuned in view of the application and the bridge queue sizes. Such applications include those concerned with raw bandwidth (such as disk storage), and those that are sensitive to latency (such as networking and videoconferencing). The embodiments of the invention feature a control register that specifies storage conditions to be met by the read and write queues of the bridge. The programmed storage conditions are trigger points which cause the bridge to transfer data into or remove data from the queues during read and write transactions in order to promote the performance (throughput or latency) desired from the bridge.

Inventors: Davis; Barry R. (Portland, OR), Eskandari; Nick G. (Chandler, AZ)

Assignee: Intel Corporation

International Classification: G06F 13/40 (20060101); G06F 013/00 ()

Expiration Date: 10/02/2018