Patent Number: 6,298,410

Title: Apparatus and method for initiating hardware priority management by software controlled register access

Abstract: An apparatus and method for controlling interrupts in a computer are disclosed, in which programmable software operates to control when data concerning the interrupt having highest priority is to be provided, and hardware logic operates to control how that data is provided. An interrupt vector register is included in the computer CPU. The interrupt vector register does not act like the typical register. It is not a physical register, and cannot be written to. A read to this register by the programmable software, triggers the hardware logic. Once triggered, this logic performs certain control tasks, the end result of which is returning to the programmable software, a vector corresponding to the interrupt having highest priority. The programmable software can implement various software policies, in addition to the hardware policy implemented by the hardware logic.

Inventors: Jayakumar; Muthurajan (Sunnyvale, CA), Goru; Vijay Kumar (San Jose, CA), Eakambaram; Ravi (San Jose, CA)

Assignee: Intel Corporation

International Classification: G06F 13/20 (20060101); G06F 13/24 (20060101); G06F 013/24 (); G06F 013/26 (); G06F 013/34 ()

Expiration Date: 10/02/2018